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ASAHI KASEI
[AK5701]
PLL & MIC-AMP
AK5701 ALC(Auto Level Control) PLL AK5701 24pin QFN
16-Bit Stereo ADC
16bit A/D AK5701 DSP
AK5701
1. 2.
: 16bits - ADC 2 or
(+30dB/+15dB or 0dB) : 1.8Vpp@VA=3.0V (= 0.6 x AVDD) : S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB HPF (fc=3.4Hz@fs=44.1kHz) - Digital ALC (Automatic Level Control) (+36dB -54dB, 0.375dB Step, Mute) 3. : - PLL Slave Mode (EXLRCK pin): 7.35kHz 48kHz - PLL Slave Mode (EXBCLK pin): 7.35kHz 48kHz - PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz - PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz - EXT Master/Slave Mode: 7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs) 4. PLL : - MCKI pin: 27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz, 11.2896MHz - EXLRCK pin: 1fs - EXBCLK pin: 32fs/64fs 5. 6. : MSB First, 2's compliment - DSP Mode, 16bit , I2S 7. P :3 8. : - AVDD: 2.4 3.6V - DVDD: 1.6 3.6V 9. : 8mA 10. Ta = -30 85C 11. : 24pin QFN (4mm x 4mm)
MS0404-J-00 -1-
2005/08
ASAHI KASEI
[AK5701]
LIN1 RIN1 LIN2 RIN2 MPWR VCOM AVDD AVSS VCOC PLL S E L ALC or HPF MIX IVOL Audio I/F Controller S E L
DVDD DVSS PDN LRCK BCLK SDTO
ADC
Control Register
EXLRCK EXBCLK EXSDTI
MCKO MCKI
CSP
CSN CCLK CDTI
Figure 1.
MS0404-J-00 -2-
2005/08
ASAHI KASEI
[AK5701]
AK5701VN AKD5701
-30 +85C AK5701
24pin QFN (0.5mm pitch)
18
17
16
15
14
MPWR RIN2 LIN2 RIN1 LIN1 VCOC
19 20 21 22 23 24 1 2 3 4 5 6
13 12 11
EXBCLK
CCLK
MCKI
CDTI
CSN
PDN
EXLRCK EXSDTI MCKO CSP SDTO LRCK
AK5701VN
Top View
10 9 8 7
VCOM
DVDD
AVDD
DVSS
AVSS
AK5355VN
AK5355VN +15dB/0dB ALC I/F PLL Left justified, I2S DSP Mode, Left justified, I2S AK5701 +30dB/+15dB/0dB
BCLK
2.1 3.6V 20pin QFN (4.2mm x 4.2mm)
AVDD=2.4 3.6V DVDD=1.6 3.6V 24pin QFN (4mm x 4mm)
MS0404-J-00 -3-
2005/08
ASAHI KASEI
[AK5701]
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Note 1.
Pin Name VCOM AVSS AVDD DVDD DVSS BCLK LRCK SDTO CSP MCKO EXSDTI EXLRCK EXBCLK MCKI CDTI CCLK CSN PDN MPWR RIN2 RIN+ LIN2 RIN- RIN1 LIN- LIN1 LIN+ VCOC
I/O O O O O I O I I I I I I I I O I I I I I I I I "H": "L": , 0.5 x AVDD ADC
Function
"H": CSN pin = "H" active, C1-0 = "01" "L": CSN pin = "L" active, C1-0 = "10"
(CSP pin = "H"
)
Rch 2 Rch Lch 2 Rch Rch 1 Lch Lch 1 Lch PLL O AVSS (LIN1, RIN1, LIN2, RIN2)
(MDIF2 bit = "0") (MDIF2 bit = "1") (MDIF2 bit = "0") (MDIF2 bit = "1") (MDIF1 bit = "0") (MDIF1 bit = "1") (MDIF1 bit = "0") (MDIF1 bit = "1")
Analog Digital
MPWR, VCOC, LIN1/LIN+, RIN1/LIN-, LIN2/RIN-, RIN2/RIN+ BCLK, LRCK, SDTO, MCKO MCKI, EXBCLK, EXLRCK, EXSDTI
DVSS
MS0404-J-00 -4-
2005/08
ASAHI KASEI
[AK5701]
(AVSS, DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital |AVSS - DVSS| (Note 3) Input Current, Any Pin Except Supplies Analog Input Voltage (Note 4) Digital Input Voltage (Note 5) Ambient Temperature (powered applied) Storage Temperature
Symbol AVDD DVDD GND IIN VINA VIND Ta Tstg
min -0.3 -0.3 -0.3 -0.3 -30 -65
max 4.6 4.6 0.3 10 AVDD+0.3 DVDD+0.3 85 150
Units V V V mA V V C C
Note 2. Note 3. AVSS DVSS Note 4. LIN1/LIN+, RIN1/LIN-, LIN2/RIN-, RIN2/RIN+ pins Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins
:
(AVSS, DVSS=0V; Note 2) Parameter Power Supplies Analog (Note 6) Digital Note 2. Note 6. AVDD, DVDD DVDD
Symbol AVDD DVDD
min 2.4 1.6
typ 3.0 3.0
Max 3.6 AVDD
Units V V
DVDD
OFF
AVDD AVDD
OFF OFF
:
MS0404-J-00 -5-
2005/08
ASAHI KASEI
[AK5701]
(Ta=25C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) Min Typ max Units Parameter MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = "0" (Single-ended inputs) Input MGAIN1-0 bits = "00" 40 60 80 k Resistance MGAIN1-0 bits = "01" or "10" 20 30 40 k MGAIN1-0 bits = "00" 0 dB Gain MGAIN1-0 bits = "01" +15 dB MGAIN1-0 bits = "10" +30 dB MIC Amplifier: LIN+, LIN-, RIN+, RIN- pins; MDIF1 = MDIF2 bits = "1" (Full-differential input) Input Voltage (Note 7) MGAIN1-0 bits = "01" 0.37 Vpp MGAIN1-0 bits = "10" 0.066 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 8) 2.02 2.25 2.48 V Load Resistance 0.5 k Load Capacitance 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins (Single-ended inputs) ADC IVOL, MGAIN=+15dB, IVOL=0dB, ALC=OFF Resolution 16 Bits MGAIN=+30dB 0.057 Vpp Input Voltage (Note 9) MGAIN=+15dB 0.27 0.32 0.37 Vpp MGAIN=0dB 1.53 1.80 2.07 Vpp 67 77 dB S/(N+D) (-0.5dBFS) (Note 10) 79 87 dB D-Range (-60dBFS, A-weighted) (Note 11) S/N (A-weighted) (Note 11) 79 87 dB Interchannel Isolation (Note 12) 80 90 dB MGAIN=+30dB 0.2 dB Interchannel Gain Mismatch MGAIN=+15dB 0.2 1.0 dB MGAIN=0dB 0.2 0.5 dB Power Supplies: Power Supply Current: AVDD+DVDD Power Up (PDN pin = "H") (Note 13) 8 12 mA Power Down (PDN pin = "L") (Note 14) 1 20 A AC MGAIN1-0 bits = "00" LIN+, LIN-, RIN+, RIN- pin AVDD Vin = |(L/RIN+) - (L/RIN-)| = 0.123 x AVDD (max)@MGAIN1-0 bits = "01", 0.022 x AVDD (max)@MGAIN1-0 bits = "10". ADC Note 8. AVDD Vout = 0.75 x AVDD (typ) Note 9. AVDD Vin = 0.107 x AVDD (typ)@MGAIN1-0 bits = "01" (+15dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = "00" (0dB) Note 10. 78dB(typ)@MGAIN=0dB, 72dB(typ)@MGAIN=+30dB Note 11. 89dB(typ)@MGAIN=0dB, 77dB(typ)@MGAIN=+30dB Note 12. 100dB(typ)@MGAIN=0dB, 80dB(typ)@MGAIN=+30dB Note 13. PLL Master Mode (MCKI=12MHz) PMADL = PMADR = PMVCM = PMPLL = PMMP = M/S bits = "1", MCKO = "0" MPWR pin 0mA AVDD=6.4mA(typ), DVDD=1.6mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = "0") : AVDD=5.7mA(typ), DVDD=1.3mA(typ). Bypass Mode (THR bit = "1", PMADL = PMADR = M/S bits = "0"), fs=8kHz : AVDD=1A(typ), DVDD=150A(typ). Note 14. DVDD DVSS Note 7.
MS0404-J-00 -6-
2005/08
ASAHI KASEI
[AK5701]
(Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; fs=44.1kHz) Parameter Symbol ADC Digital Filter (Decimation LPF): Passband (Note 15) PB 0.1dB -1.0dB -3.0dB Stopband (Note 15) SB Passband Ripple PR Stopband Attenuation SA Group Delay (Note 16) GD Group Delay Distortion GD ADC Digital Filter (HPF): HPF1-0 bits = "00" Frequency Response (Note 15) -3.0dB FR -0.5dB -0.1dB Note 15. Note 16. fs ( PB=20.0kHz(@-1.0dB)
min 0 25.7 65 )
typ 20.0 21.1 18 0 3.4 10 22
max 17.4 0.1 -
Units kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz
0.454 x fs
(ADC)
1kHz 16
DC (Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V) Parameter Symbol High-Level Input Voltage Except CSP pin; 2.2V DVDD 3.6V VIH Except CSP pin; 1.6V DVDD <2.2V VIH CSP pin VIH Low-Level Input Voltage Except CSP pin; 2.2V DVDD 3.6V VIL Except CSP pin; 1.6V DVDD <2.2V VIL CSP pin VIL High-Level Output Voltage (Iout= -200A) VOH Low-Level Output Voltage (Iout= 200A) VOL Input Leakage Current (Note 17) Iin
Note 17. CSP pin = "H" CCLK pin
min 70%DVDD 80%DVDD 90%DVDD DVDD-0.2 -
typ (typ. 100k)
max 30%DVDD 20%DVDD 10%DVDD 0.2 10
Units V V V V V V V V A
MS0404-J-00 -7-
2005/08
ASAHI KASEI
[AK5701]
(Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; CL=20pF) Parameter Symbol PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK Pulse Width Low tCLKL Pulse Width High tCLKH MCKO Output Timing Frequency fMCK Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 256fs at fs=32kHz, 29.4kHz dMCK LRCK Output Timing Frequency Except DSP Mode 1 fs DSP Mode 1 (Note 18) fsd DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BCLK Output Timing Period BCKO1-0 bit = "01" tBCK BCKO1-0 bit = "10" tBCK Duty Cycle dBCK PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK Pulse Width Low tCLKL Pulse Width High tCLKH MCKO Output Timing Frequency fMCK Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 256fs at fs=32kHz, 29.4kHz dMCK EXLRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH PLL Slave Mode (PLL Reference Clock = EXLRCK pin) EXLRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH Note 18. 7.35kHz 48kHz
min
typ
max
Units
11.2896 0.4/fCLK 0.4/fCLK 0.2352 40 -
50 33
27 12.288 60 -
MHz ns ns MHz % %
7.35 14.7 -
tBCK 50 1/(32fs) 1/(64fs) 50
48 96 -
kHz kHz ns % ns ns %
11.2896 0.4/fCLK 0.4/fCLK 0.2352 40 7.35 tBCK-60 45 1/(64fs) 0.4 x tBCK 0.4 x tBCK
50 33 -
27 12.288 60 48 1/fs - tBCK 55 1/(32fs) -
MHz ns ns MHz % % kHz ns % ns ns ns
7.35 tBCK-60 45 1/(64fs) 240 240
-
48 1/fs - tBCK 55 1/(32fs) -
kHz ns % ns ns ns
MS0404-J-00 -8-
2005/08
ASAHI KASEI
[AK5701]
Parameter Symbol PLL Slave Mode (PLL Reference Clock = EXBCLK pin) EXLRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period PLL3-0 bits = "0010" tBCK PLL3-0 bits = "0011" tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Slave Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH EXLRCK Input Timing Frequency 256fs fs 512fs fs 1024fs fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Master Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Output Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BCLK Output Timing Period BCKO1-0 bit = "01" tBCK BCKO1-0 bit = "10" tBCK Duty Cycle dBCK
min
typ
max
Units
7.35 tBCK-60 45 0.4 x tBCK 0.4 x tBCK
1/(32fs) 1/(64fs) -
48 1/fs - tBCK 55 -
kHz ns % ns ns ns ns
1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK 7.35 7.35 7.35 tBCK-60 45 312.5 130 130
-
12.288 13.312 13.312 48 26 13 1/fs - tBCK 55 -
MHz MHz MHz ns ns kHz kHz kHz ns % ns ns ns
1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK 7.35 -
tBCK 50 1/(32fs) 1/(64fs) 50
12.288 13.312 13.312 48 -
MHz MHz MHz ns ns kHz ns % ns ns %
MS0404-J-00 -9-
2005/08
ASAHI KASEI
[AK5701]
Parameter Audio Interface Timing (DSP Mode) Master Mode LRCK "" to BCLK "" (Note 19) LRCK "" to BCLK "" (Note 20) BCLK "" to SDTO (BCKP bit = "0") BCLK "" to SDTO (BCKP bit = "1") Slave Mode EXLRCK "" to EXBCLK "" (Note 19) EXLRCK "" to EXBCLK "" (Note 20) EXBCLK "" to EXLRCK "" (Note 19) EXBCLK "" to EXLRCK "" (Note 20) EXBCLK "" to SDTO (BCKP bit = "0") EXBCLK "" to SDTO (BCKP bit = "1") Audio Interface Timing (Left justified & I2S) Master Mode BCLK "" to LRCK Edge (Note 21) LRCK Edge to SDTO (MSB) (Except I2S mode) BCLK "" to SDTO Slave Mode EXLRCK Edge to EXBCLK "" (Note 21) EXBCLK "" to EXLRCK Edge (Note 21) EXLRCK Edge to SDTO (MSB) (Except I2S mode) EXBCLK "" to SDTO Note 19. MSBS, BCKP bits = "00" or "11" Note 20. MSBS, BCKP bits = "01" or "10" Note 21. EXLRCK
Symbol
min
typ
Max
Units
tDBF tDBF tBSD tBSD tLRB tLRB tBLR tBLR tBSD tBSD
0.5 x tBCK - 40 0.5 x tBCK - 40 -70 -70 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK -
0.5 x tBCK 0.5 x tBCK -
0.5 x tBCK + 40 0.5 x tBCK + 40 70 70 80 80
ns ns ns ns ns ns ns ns ns ns
tMBLR tLRD tBSD tLRB tBLR tLRD tBSD
-40 -70 -70 50 50 -
-
40 70 70 80 80
ns ns ns ns ns ns ns
EXBCLK
""
MS0404-J-00 - 10 -
2005/08
ASAHI KASEI
[AK5701]
Parameter Control Interface Timing (CSP pin = "L") CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Control Interface Timing (CSP pin = "H") CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "L" Time CSN "" to CCLK "" CCLK "" to CSN "" Power-down & Reset Timing PDN Pulse Width (Note 22) PMADL or PMADR "" to SDTO valid (Note 23) HPF1-0 bits = "00" HPF1-0 bits = "01" HPF1-0 bits = "10" Note 22. AK5701 PDN pin = "L" Note 23. PMADL bit PMADR bit
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tPD tPDV tPDV tPDV
min 142 56 56 28 28 150 50 50 142 56 56 28 28 150 50 50 150 -
typ 3088 1552 784
max -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1/fs 1/fs 1/fs
LRCK
""
MS0404-J-00 - 11 -
2005/08
ASAHI KASEI
[AK5701]
1/fCLK VIH MCKI VIL tCLKH 1/fs tCLKL
LRCK tLRCKH tBCK tLRCKL
50%DVDD
Duty = tLRCKH x fs x 100 tLRCKL x fs x 100
BCLK tBCKH tBCKL 1/fMCK
50%DVDD
dBCK = tBCKH / tBCK x 100 tBCKL / tBCK x 100
MCKO tMCKL
50%DVDD dMCK = tMCKL x fMCK x 100
Figure 2. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK tDBF tBCK dBCK BCLK (BCKP = "0")
50%DVDD
50%DVDD
BCLK (BCKP = "1") tBSD
50%DVDD
SDTO
MSB
50%DVDD
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = "0")
MS0404-J-00 - 12 -
2005/08
ASAHI KASEI
[AK5701]
tLRCKH
LRCK tDBF tBCK dBCK BCLK (BCKP = "1")
50%DVDD
50%DVDD
BCLK (BCKP = "0") tBSD
50%DVDD
SDTO
MSB
50%DVDD
Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = "1")
LRCK
50%DVDD
tMBLR
tBCKL 50%DVDD
BCLK tLRD
tBSD
SDTO
50%DVDD
Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)
MS0404-J-00 - 13 -
2005/08
ASAHI KASEI
[AK5701]
1/fs VIH VIL tLRCKH tBCK VIH EXBCLK (BCKP = "0") tBCKH tBCKL VIH EXBCLK (BCKP = "1") VIL VIL tBLR
EXLRCK
Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 0)
1/fs VIH VIL tLRCKH tBCK VIH EXBCLK (BCKP = "1") tBCKH tBCKL VIH EXBCLK (BCKP = "0") VIL VIL tBLR
EXLRCK
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 1)
MS0404-J-00 - 14 -
2005/08
ASAHI KASEI
[AK5701]
1/fCLK VIH MCKI VIL tCLKH 1/fs VIH EXLRCK VIL tLRCKH tBCK tLRCKL Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH EXBCLK VIL tBCKH fMCK tBCKL tCLKL
MCKO tMCKL
50%DVDD
dMCK = tMCKL x fMCK x 100
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
tLRCKH VIH EXLRCK tLRB VIL
VIH EXBCLK VIL (BCKP = "0") VIH EXBCLK (BCKP = "1") tBSD VIL
SDTO
MSB
50%DVDD
Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)
MS0404-J-00 - 15 -
2005/08
ASAHI KASEI
[AK5701]
tLRCKH VIH EXLRCK tLRB VIL
VIH EXBCLK (BCKP = "1") VIH EXBCLK (BCKP = "0") tBSD VIL VIL
SDTO
MSB
50%DVDD
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1)
1/fCLK VIH MCKI VIL tCLKH 1/fs VIH EXLRCK VIL tLRCKH tBCK VIH EXBCLK VIL tBCKH tBCKL tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tCLKL
Figure 11. Clock Timing (EXT Slave mode)
MS0404-J-00 - 16 -
2005/08
ASAHI KASEI
[AK5701]
VIH EXLRCK VIL tBLR tLRB VIH EXBCLK VIL tLRD tBSD
SDTO
MSB
50%DVDD
Figure 12. Audio Interface Timing (PLL/EXT Slave mode)
MS0404-J-00 - 17 -
2005/08
ASAHI KASEI
[AK5701]
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCCK tCDH VIH R/W VIL
Figure 13. WRITE Command Input Timing (CSP pin = "L")
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL
Figure 14. WRITE Data Input Timing (CSP pin = "L")
MS0404-J-00 - 18 -
2005/08
ASAHI KASEI
[AK5701]
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCCK tCDH VIH R/W VIL
Figure 15. WRITE Command Input Timing (CSP pin = "H")
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL
Figure 16. WRITE Data Input Timing (CSP pin = "H")
MS0404-J-00 - 19 -
2005/08
ASAHI KASEI
[AK5701]
PMADL bit or PMADR bit tPDV
SDTO
50%DVDD
Figure 17. Power Down & Reset Timing 1
tPD PDN VIL
Figure 18. Power Down & Reset Timing 2
MS0404-J-00 - 20 -
2005/08
ASAHI KASEI
[AK5701]
I/F
5
(See Table 1 and Table 2.) Figure Figure 19 Figure 21 Figure 20 Figure 22 Figure 23 MCKO pin
Mode PMPLL bit M/S bit PLL3-0 bits PLL Master Mode (Note 24) 1 1 See Table 4 PLL Slave Mode 1 1 0 See Table 4 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 (PLL Reference Clock: EXLRCK or EXBCLK pin) EXT Slave Mode 0 0 x EXT Master Mode (Note 25) 0 1 x Note 24. PLL Master Mode M/S bit = "1", PMPLL bit = "0", MCKO bit = "1" Note 25. EXT Master Mode Figure 49 Table 1. Clock Mode Setting (x: Don't care) MCKO bit 0 PLL Master Mode PLL Slave Mode (PLL Reference Clock: MCKI pin) PLL Slave Mode (PLL Reference Clock: EXLRCK or EXBCLK pin) EXT Slave Mode EXT Master Mode 1 0 1 0 0 0 MCKO pin "L" PS1-0 bits "L" PS1-0 bits MCKI pin PLL3-0 bits
Mode
BCLK pin, LRCK pin, EXBCLK pin EXLRCK pin BCLK pin LRCK pin (BCKO1-0 (1fs) (Note 26) bits ) EXBCLK pin EXLRCK pin (1fs) ( 32fs) EXBCLK pin EXLRCK pin (PLL3-0 bits (1fs) ) EXBCLK pin EXLRCK pin (1fs) ( 32fs) BCLK pin LRCK pin (BCKO1-0 (1fs) bits ) 2fs
PLL3-0 bits
"L" "L" "L"
GND FS1-0 bits FS1-0 bits
Table 2. Clock pins state in Clock Mode Note 26. PLL Master Mode DSP Mode 1 LRCK
AK5701 M/S bit "1"
M/S bit (PDN pin = "L")
"1"
"0"
M/S bit 0 1
Mode Slave Mode EXBCLK, EXLRCK Master Mode BCLK, LRCK Table 3. Select Master/Salve Mode
Default
MS0404-J-00 - 21 -
2005/08
ASAHI KASEI
[AK5701]
PLL
PMPLL bit = "1" PLL PLL FS3-0 bit, PLL3-0 bit PMPLL bit "0" "1" Table 4
1) PLL Mode
Mode
PLL3 bit 0 0 0 0 0 0 0 1 1 1 1 1 1
PLL2 bit 0 0 0 1 1 1 1 0 0 1 1 1 1
PLL1 bit 0 1 1 0 0 1 1 0 0 0 0 1 1
PLL0 bit 0 0 1 0 1 0 1 0 1 0 1 0 1
PLL EXLRCK pin EXBCLK pin EXBCLK pin 1fs 32fs 64fs
0 2 3 4 5 6 7 8 9 12 13 14 15
Others
MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 19.2MHz MCKI pin 12MHz (Note 27) MCKI pin 13.5MHz MCKI pin 27MHz MCKI pin 13MHz MCKI pin 26MHz Others N/A Table 4. Setting of PLL Mode (fs: Sampling Frequency) Note 27. PLL3-0 bits = "0110" "1001" Table 5
VCOC pin R,C R[] C[F] 6.8k 220n 10k 4.7n 10k 10n 10k 4.7n 10k 10n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n 10k 220n 10k 220n
PLL (max) 80ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 60ms 60ms
Default
2) PLL Mode MCKI Mode 0 1 2 3
Sampling Frequency 8kHz 12kHz 16kHz 24kHz 7.35kHz 4 0 7.349918kHz (Note 28) 11.025kHz 0 1 1 5 0 11.024877kHz (Note 28) 14.7kHz 0 1 0 6 1 14.69984kHz (Note 28) 22.05kHz 0 7 1 1 1 22.04975kHz (Note 28) 32kHz 10 1 0 1 0 48kHz 11 1 0 1 1 29.4kHz 1 14 1 1 0 29.39967kHz (Note 28) 44.1kHz 1 15 1 1 1 Default 44.0995kHz (Note 28) Others Others N/A Table 5. Setting of Sampling Frequency at PMPLL bit = "1" and Reference Clock=MCKI pin Note 28. PLL3-0 bits = "1001"
Table 5 FS3 bit 0 0 0 0 0
FS2 bit 0 0 0 0 1
FS1 bit 0 0 1 1
FS0 bit 0 1 0 1 0
MS0404-J-00 - 22 -
2005/08
ASAHI KASEI
[AK5701]
EXLRCK or EXBCLK FS3 bit Mode
(Table 6) Sampling Frequency FS1 bit FS0 bit Range 0 0 Don't care Don't care 7.35kHz fs 12kHz 0 0 1 Don't care Don't care 12kHz < fs 24kHz 1 1 Don't care Don't care Don't care 24kHz < fs 48kHz 2 Default Others Others N/A Table 6. Setting of Sampling Frequency at PMPLL bit = "1" and Reference=EXLRCK/EXBCLK FS2 bit
FS3, FS2 bit
PLL
1) PLL Master Mode (PMPLL bit = "1", M/S bit = "1") PMPLL bit = "0" MCKO pin "L" "1" (See Table 7) PLL BCLK LRCK Lch MSBS bit = "0", BCKP bit = "1" MSBS bit = "1", BCKP 2 1/(256fs) BCLK, PLL BCLK LRCK "L" MCKO bit = "0" MCKO
bit = "1" MCKO pin
DSP Mode 0, 1 bit = "0" BCLK
PMPLL bit = "0" "1" DSP Mode 0, 1 1 "H"
PMPLL bit = "0" LRCK PLL State "L"
MCKO pin BCLK pin LRCK pin MCKO bit = "0" MCKO bit = "1" "L" Output "L" Output "L" Output PMPLL bit "0" "1" "L" Output PLL Unlock ( ) "L" Output 1fs Output (*) See Table 9 See Table 10 PLL Lock Table 7. Clock Operation at PLL Master Mode (PMPLL bit = "1", M/S bit = "1") * DSP Mode 1 LRCK 2fs 2) PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") PMPLL bit = "0" PLL PLL State "1" PLL PLL MCKO pin ADC MCKO Table 9
MCKO pin MCKO bit = "0" MCKO bit = "1" "L" Output PMPLL bit "0" "1" "L" Output PLL Unlock ( ) "L" Output See Table 9 PLL Lock Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = "1", M/S bit = "0")
MS0404-J-00 - 23 -
2005/08
ASAHI KASEI
[AK5701]
PLL Master Mode (PMPLL bit = "1", M/S bit = "1")
11.2896MHz, 12MHz , 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz PLL MCKO, BCLK, LRCK (MCKO) PS1-0 bit (Table 9) MCKO bit ON/OFF BCLK BCKO1-0 bits 32fs or 64fs (See Table 10)
11.2896MHz, 12MHz, 12.288MHz, 13MHz 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK5701
MCKI MCKO BCLK LRCK SDTO 256fs/128fs/64fs/32fs 32fs, 64fs 1fs
DSP or P
MCLK BCLK LRCK SDTI
Figure 19. PLL Master Mode Mode 0 1 2 3 PS1 bit 0 0 1 1 Table 9. MCKO PS0 bit 0 1 0 1 (PLL MCKO pin 256fs Default 128fs 64fs 32fs , MCKO bit = "1")
BCKO1 bit BCKO0 bit BCLK 0 0 N/A 0 1 32fs Default 1 0 64fs 1 1 N/A Table 10. BCLK Output Frequency at Master Mode
MS0404-J-00 - 24 -
2005/08
ASAHI KASEI
[AK5701]
PLL Slave Mode (PMPLL bit = "1", M/S bit = "0")
MCKI, EXBCLK or EXLRCK pin PLL a) PLL FS3-0 bit PLL PLL3-0 bit AK5701 (Table 4)
: EXBCLK or EXLRCK pin 7.35kHz 48kHz (See Table 6.)
AK5701 DSP or P
MCKI EXBCLK EXLRCK SDTO 32fs, 64fs 1fs BCLK LRCK SDTI
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: EXLRCK or EXBCLK pin) b) PLL MCKO MCKO bit 5)
11.2896MHz, 12MHz, 12.288MHz, 13MHz 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
: MCKI pin EXBCLK, EXLRCK ON/OFF MCKO EXLRCK (MCKO pin) PS1-0 bit (Table 9) FS3-0 bit
(See Table
AK5701
MCKI MCKO EXBCLK EXLRCK SDTO 256fs/128fs/64fs/32fs
DSP or P
MCLK BCLK LRCK SDTI
32fs
1fs
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: MCKI pin) ADC (PMADL bit = "1" or PMADR bit = "1") (MCKI, EXBCLK, EXLRCK)
(PMADL=PMADR bits = "0")
MS0404-J-00 - 25 -
2005/08
ASAHI KASEI
[AK5701]
EXT Slave Mode (PMPLL bit = "0", M/S bit = "0")
PMPLL bit "0" ADC MCKI EXLRCK FS1-0 bit Mode 0 1 2 3 FS3-2 bits FS1 bit MCKI pin PLL CODEC I/F MCKI (256fs, 512fs or 1024fs), EXBCLK (32fs), EXLRCK(fs) MCKI (See Table 11) FS0 bit (EXT Slave Mode)
MCKI Input Sampling Frequency Frequency Range Don't care 0 0 256fs 7.35kHz 48kHz Don't care 0 1 1024fs 7.35kHz 13kHz Don't care 1 0 512fs 7.35kHz 26kHz Don't care 1 1 256fs 7.35kHz 48kHz Table 11. EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") MCKI (MCKI, EXBCLK, EXLRCK)
Default
ADC
(PMADL bit = "1" or PMADR bit = "1")
(PMADL=PMADR bits = "0")
AK5701
MCKO 256fs, 512fs or 1024fs MCKI EXBCLK EXLRCK SDTO 32fs 1fs MCLK BCLK LRCK SDTI
DSP or P
Figure 22. EXT Slave Mode
MS0404-J-00 - 26 -
2005/08
ASAHI KASEI
[AK5701]
EXT Master Mode (PMPLL bit = "0", M/S bit = "1", TE3-0 bits = "0101", TMASTER bit = "1")
Figure 49 MCKI pin PLL (256fs, 512fs or 1024fs) Mode 0 1 2 3 FS3-2 bits
Don't care Don't care Don't care Don't care
ADC MCKI FS1 bit FS1-0 bit FS0 bit
(EXT Master Mode) MCKI (See Table 12) Sampling Frequency Range 7.35kHz 48kHz 7.35kHz 13kHz 7.35kHz 26kHz 7.35kHz 48kHz
MCKI Input Frequency 0 0 256fs 0 1 1024fs 1 0 512fs 1 1 256fs Table 12. EXT Master Mode MCKI MCKI
Default
ADC MCKI
(PMADL bit = "1" or PMADR bit = "1")
MCKI
(PMADL=PMADR bits = "0")
AK5701
MCKO 256fs, 512fs or 1024fs MCKI BCLK LRCK SDTO 32fs or 64fs 1fs MCLK BCLK LRCK SDTI
DSP or P
Figure 23. EXT Master Mode BCKO1 bit BCKO0 bit BCLK 0 0 N/A 0 1 32fs Default 1 0 64fs 1 1 N/A Table 13. BCLK Output Frequency at Master Mode
MS0404-J-00 - 27 -
2005/08
ASAHI KASEI
[AK5701]
THR bit = "1", M/S bit = "0", PMADL bit = "0", PMADR bit = "0" LRCK, BCLK, SDTO pins THR bit = "1", M/S bit = "0" LRCK, BCLK pins PMADL bit = "1" or PMADR bit = "1" SDTO pin ADC
EXLRCK, EXBCLK, EXSDTI pins
EXLRCK, EXBCLK pins
THR bit
M/S bit 0
0 1 0 1 1
PMADL bit PMADR bit "00" "01"/"10"/"11" "00" "01"/"10"/"11" "00" "01"/"10"/"11" "00" "01"/"10"/"11"
BCLK/LRCK
SDTO
Mode Power down Slave mode Power down Master mode Bypass mode Slave & Bypass N/A Master mode
Figure Default
"L" "L" "L" ADC data Output "L" Output ADC data EXBCLK/EXLRCK EXSDTI EXBCLK/EXLRCK ADC data N/A N/A Output ADC data Table 14. Bypass Mode Select
Figure 24 Figure 25
DSP or P
32fs BCLK LRCK SDTI 1fs
AK5701
32fs BCLK LRCK SDTO EXBCLK EXLRCK EXSDTI 1fs
DSP or P
BCLK LRCK SDTO
Figure 24. Bypass Mode
DSP or P
32fs BCLK LRCK SDTI 1fs
AK5701
32fs BCLK LRCK SDTO EXBCLK EXLRCK LIN/RIN 1fs
DSP or P
BCLK LRCK
Analog In
Figure 25. Slave & Bypass Mode
MS0404-J-00 - 28 -
2005/08
ASAHI KASEI
[AK5701]
4
(Table 15)
DIF1-0 bit
MSB
2's
DSP Mode 1 PLL Master Mode EXLRCK, EXBCLK, SDTO BCLK/EXBCLK "" Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO DSP Mode 0 DSP Mode 1
Mode 2
LRCK, BCLK, SDTO Mode 3 SDTO
BCLK, EXBCLK 32fs 32fs 32fs I2S 32fs Table 15. Audio Interface Format I/F
Figure See Table 16 Figure 34 Figure 35 Default
Mode 0, 1 (DSP
0, 1)
BCKP, MSBS bit
BCKP bit = "0" BCKP bit = "1" MSBS bit DIF1 MSB DIF0
SDTO SDTO
BCLK/EXBCLK BCLK/EXBCLK BCLK/EXBCLK
"" ""
MSBS 0 0
BCKP 0 1 0
0
0
1
1 0 0 0 1 1
1 0 1 0
1
1
Audio Interface Format SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" (Figure 26) SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" (Figure 27) SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 28) SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 29) SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" (Figure 30) SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" (Figure 31) SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 32) SDTO MSB LRCK/EXLRCK "" 1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 33) Table 16. Audio Interface Format in Mode 0, 1 8bit 16bit "-1"
Default
ADC "-1" (128)
16bit 8bit "-256"
"-1"
8bit 8bit
DAC 16bit
16bit 16bit
MS0404-J-00 - 29 -
2005/08
ASAHI KASEI
[AK5701]
EXLRCK LRCK
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
SDTO(o)
1/fs 15:MSB, 0:LSB
1/fs
Figure 26. Mode 0 Timing (BCKP = "0", MSBS = "0", M/S = "0" or "1")
EXLRCK LRCK
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
SDTO(o)
1/fs 15:MSB, 0:LSB
1/fs
Figure 27. Mode 0 Timing (BCKP = "1", MSBS = "0", M/S = "0" or "1")
EXLRCK LRCK
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
SDTO(o)
1/fs 15:MSB, 0:LSB
1/fs
Figure 28. Mode 0 Timing (BCKP = "0", MSBS = "1", M/S = "0" or "1")
EXLRCK LRCK
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
Lch
15 14 8 2 1 0
Rch
15 14 2 1 0
SDTO(o)
1/fs 15:MSB, 0:LSB
1/fs
Figure 29. Mode 0 Timing (BCKP = "1", MSBS = "1", M/S = "0" or "1")
MS0404-J-00 - 30 -
2005/08
ASAHI KASEI
[AK5701]
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch Rch
8
8
SDTO(o)
15
0
0
15 14
1 2
8
14
7
15
6
16
5
17
4
18
3
29
2
30
1
31
0
0
15 14
1 2
8
8
8
14
7
15
6
16
5
17
4
18
3
13
2
30
1
31
0
BCLK(64fs)
Lch Rch
8 2 1 0 15 14 8 2 1 0
SDTO(o)
15 14
1/fs 15:MSB, 0:LSB
Figure 30. Mode 1 Timing (BCKP = "0", MSBS = "0", M/S = "1")
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch Rch
8
8
SDTO(o)
15
0
0
15 14
1 2
8
14
7
15
6
16
5
17
4
18
3
29
2
30
1
31
0
0
15 14
1 2
8
8
8
14
7
15
6
16
5
17
4
18
3
13
2
30
1
31
0
BCLK(64fs)
Lch Rch
8 2 1 0 15 14 8 2 1 0
SDTO(o)
15 14
1/fs 15:MSB, 0:LSB
Figure 31. Mode 1 Timing (BCKP = "1", MSBS = "0", M/S = "1")
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch Rch
8
8
SDTO(o)
15
0
0
15 14
1 2
8
14
7
15
6
16
5
17
4
18
3
29
2
30
1
31
0
0
15 14
1 2
8
8
8
14
7
15
6
16
5
17
4
18
3
13
2
30
1
31
0
BCLK(64fs)
Lch Rch
8 2 1 0 15 14 8 2 1 0
SDTO(o)
15 14
1/fs 15:MSB, 0:LSB
Figure 32. Mode 1 Timing (BCKP = "0", MSBS = "1", M/S = "1")
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch Rch
8
8
SDTO(o)
15
0
0
15 14
1 2
8
14
7
15
6
16
5
17
4
18
3
29
2
30
1
31
0
0
15 14
1 2
8
8
8
14
7
15
6
16
5
17
4
18
3
13
2
30
1
31
0
BCLK(64fs)
Lch Rch
8 2 1 0 15 14 8 2 1 0
SDTO(o)
15 14
1/fs 15:MSB, 0:LSB
Figure 33. Mode 1 Timing (BCKP = "1", MSBS = "1", M/S = "1")
MS0404-J-00 - 31 -
2005/08
ASAHI KASEI
[AK5701]
EXLRCK LRCK
0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1
EXBCLK(32fs) BCLK(32fs)
SDTO(o)
0
15 14 13
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15 14 13
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15
1
EXBCLK(64fs) BCLK(64fs)
SDTO(o)
15 14 13
13 2
1
0
15 14 13
1
2
1
0
15
15:MSB, 0:LSB Lch Data Rch Data
Figure 34. Mode 2
(
, M/S = "0" or "1")
EXLRCK LRCK
EXBCLK(32fs) BCLK(32fs)
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
4
9
10
11
12
13
14
15
0
1
SDTO(o)
0
0
1
15
2
14 13
3 4
7
14
7
15
6
16
5
17
4
18
3
2
31
1
0
0
1
15 14 13
2 3 4
7
14
7
15
6
16
5
17
4
18
3
2
31
1
0
0
1
EXBCLK(64fs) BCLK(64fs)
SDTO(o)
15 14 13
2
1
0
15 14 13
2
2
1
0
15:MSB, 0:LSB Lch Data Rch Data
Figure 35. Mode 3
(I2S, M/S = "0" or "1")
PMADL, PMADR, MIX bits ALC
ADC (ALC bit = "1")
(ALC bit = "0")
PMADL bit 0 0 1 1
PMADR bit 0 1 0
MIX bit x x x 0 1 1 Table 17.
ADC Lch data ADC Rch data All "0" All "0" Rch Input Signal Rch Input Signal Lch Input Signal Lch Input Signal Lch Input Signal Rch Input Signal (L+R)/2 (L+R)/2 (x: Don't care)
Default
MS0404-J-00 - 32 -
2005/08
ASAHI KASEI
[AK5701]
HPF
AK5701 DC HPF (fs) HPF1 bit 0 0 1 1 HPF0 bit 0 1 0 1 fc fs=44.1kHz fs=22.05kHz 3.4Hz 1.7Hz 6.8Hz 3.4Hz 13.6Hz 6.8Hz N/A N/A Table 18. HPF HPF HPF1-0 bits 3.4Hz (@fs= 44.1kHz)
fs=11.025kHz 0.85Hz 1.7Hz 3.4Hz N/A
Default
AK5701 RIN1/RIN2 LIN+, LIN-, RIN-, RIN+ pin MDIF1 bit MDIF2 bit 0 0 1 1 0 1
MDIF1, MDIF2 bit = "0" INL, INR bit LIN1/LIN2, MDIF1, MDIF2 bit = "1" LIN1, RIN1, LIN2, RIN2 pin (Figure 37) INR bit Lch 0 LIN1 0 1 LIN1 0 LIN2 1 1 LIN2 0 x LIN1 1 x N/A 0 N/A x 1 LIN+/- x x LIN+/- Table 19. MIC/Line In Path Select Rch RIN1 RIN2 RIN1 RIN2 RIN+/- N/A N/A RIN2 RIN+/-
INL bit
Default
AK5701
LIN1/LIN+ pin INL bit
RIN1/ LIN- pin MDIF1 bit
ADC Lch
INR bit RIN2/ RIN+ pin LIN2/ RIN- pin MDIF2 bit
ADC Rch
Figure 36.
MS0404-J-00 - 33 -
2005/08
ASAHI KASEI
[AK5701]
AK5701 MPWR pin 1k IN1- pin IN1+ pin 1k
MIC-Amp
Figure 37.
(MDIF1/2 bits = "1")
AK5701 (Table 20) 30k
MGAIN1-0 bit MGAIN1-0 bits = "00" typ. 60k MGAIN1-0 bits = "01", "10"
typ.
MGAIN1 bit 0 0 1 1
MGAIN0 bit 0 1 0 1 Table 20.
Input Gain 0dB +15dB +30dB N/A
Default
PMMP bit = "1" AVDD)V (typ) MPWR pin
MPWR pin min. 0.5k (Figure 38 PMMP bit MPWR pin 0 Hi-Z 1 Output Table 21.
MIC Power MPWR pin
2 )
(0.75 x min. 2k
Default
2k
2k
2k
2k
Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin
Figure 38. MIC Block Circuit
MS0404-J-00 - 34 -
2005/08
ASAHI KASEI
[AK5701]
ALC
ALC bit = "1" 1. ALC Lch, Rch LMAT1-0 bit IVL, IVR L/R ALC (L/R (Table 22) ) ALC ALC
ALC
(Table 23)
IVL, IVR
ZELMN bit = "0"( ALC ZELMN bit = "1"(
) ZTM1-0 bit
ALC (Table 24)
IVL, IVR
L/R
) ALC LMAT1-0 bit ALC bit "0"
IVL, IVR 1 step ALC
(
: 1/fs)
LMTH1 0 0 1 1
LMTH0 ALC 0 ALC Output -2.5dBFS 1 ALC Output -4.1dBFS 0 ALC Output -6.0dBFS 1 ALC Output -8.5dBFS Table 22. ALC ZELMN 0 1 LMAT1 LMAT0 0 0 0 1 1 0 1 1 x x Table 23. ALC
ALC -2.5dBFS > ALC Output -4.1dBFS -4.1dBFS > ALC Output -6.0dBFS -6.0dBFS > ALC Output -8.5dBFS -8.5dBFS > ALC Output -12dBFS
Default
ALC 1 step 2 step 4 step 8 step 1step ATT
ATT 0.375dB 0.750dB 1.500dB 3.000dB 0.375dB
Default
ZTM1 0 0 1 1
ZTM0 0 1 0 1 128/fs 256/fs 512/fs 1024/fs Table 24. ALC
8kHz 16ms 32ms 64ms 128ms
16kHz 8ms 16ms 32ms 64ms
44.1kHz 2.9ms 5.8ms 11.6ms 23.2ms
Default
MS0404-J-00 - 35 -
2005/08
ASAHI KASEI
[AK5701]
2.
ALC WTM1-0 (Table 25) (Table 22) ALC (Table 27) ZTM1-0 (Table 24) RGAIN1-0 bit (Table 26) IVL, IVR (L/R ) WTM1-0 WTM1-0 ZTM1-0 ALC IVL, IVR IVL, IVR 32H IVL, IVR ALC ( ( ) Output Signal < ( ) > Output Signal ) 30H RGAIN1-0 bit = "01"(2 steps) 0.75dB(0.375dB x 2) ALC ALC ALC ZTM1-0
ALC
ALC IVL, IVR (REF7-0)
ALC
ALC
WTM1 0 0 1 1
WTM0 0 1 0 1
ALC 8kHz 128/fs 16ms 256/fs 32ms 512/fs 64ms 1024/fs 128ms Table 25. ALC RGAIN0 0 1 0 1 Table 26. ALC 16kHz 8ms 16ms 32ms 64ms 44.1kHz 2.9ms 5.8ms 11.6ms 23.2ms Default
RGAIN1 0 0 1 1
GAIN STEP 1 step 0.375dB 2 step 0.750dB 3 step 1.125dB 4 step 1.500dB
Default
REF7-0 GAIN(dB) F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 E1H +30.0 E0H +29.625 : : 03H -53.25 02H -53.625 01H -54.0 00H MUTE Table 27. ALC
Step
0.375dB
Default
MS0404-J-00 - 36 -
2005/08
ASAHI KASEI
[AK5701]
3.
ALC ALC Comment Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data as ZTM1-0 bits Maximum gain at recovery operation Gain of IVOL Limiter ATT step Recovery GAIN step ALC enable fs=8kHz Operation -4.1dBFS Enable 16ms 16ms +30dB 0dB 1 step 1 step Enable fs=44.1kHz Operation -4.1dBFS Enable 11.6ms 11.6ms +30dB 0dB 1 step 1 step Enable
Table 28 Register Name LMTH ZELMN ZTM1-0 WTM1-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 ALC
Data 01 0 00 00 E1H 91H
Data 01 0 10 10 E1H 91H 00 00 1
00 00 1 Table 28. ALC
ALC bit = "0"
ALC PMADL = PMADR bits = "0")
(ALC
LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = -4.1dBFS Manual Mode * The value of IVOL should be the same or smaller than REF's WR (ZTM1-0, WTM1-0) (2) Addr=1AH, Data=00H ALC bit = "1" (1) Addr=18H&19H, Data=91H
WR (IVL/R7-0)
WR (REF7-0)
(3) Addr=1BH, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= "1")
(4) Addr=1CH, Data=81H
ALC Operation
Note : WR : Write Figure 39. ALC
MS0404-J-00 - 37 -
2005/08
ASAHI KASEI
[AK5701]
(
ALC bit = "0"
)
1. 2. 3.
ALC
(ZTM1-0, LMTH ) ALC
IVL7-0, IVR7-0 bit
(Table 29) ZTM1-0 bit
L/R
PMADL = PMADR bits = "0" = "1" ADC
IVL7-0, IVR7-0 bits IVOL GAIN (dB) +36.0 +35.625 +35.25 : +0.375 0.0 -0.375 : -53.25 -53.625 -54 MUTE Step
PMADL bit = "1" or PMADR bit
IVL7-0 IVR7-0 F1H F0H EFH : 92H 91H 90H : 03H 02H 01H 00H Table 29.
0.375dB
Default
MS0404-J-00 - 38 -
2005/08
ASAHI KASEI
[AK5701]
IVL7-0, IVR7-0 bit
ALC bit
ALC Status
Disable
Enable
Disable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
E1H(+30dB) (1)
E1(+30dB) --> F1(+36dB)
E1(+30dB) (2)
Internal IVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
C6H(+20dB)
Figure 40. ALC (1) ALC IVL IVR IVL7-0 bits (WTM1-0 bits) + (2) ALC IVL, IVR ALC bit = "0"
IVOL IVL ALC bit = "1"
ALC (ZTM1-0 bits) (18H, 19H) ALC Disable ALC Enable ALC bit = "1"
PDN pin AK5701 PMADL=PMADR bits = "0" (Table 30) ADC HPF1 bit 0 0 1 1 HPF0 bit 0 1 0 1 ADC
"L"
PMADL bit
PMADR bit "0" "1" ADC HPF1-0 bits = "00" 3088/fs=70.0ms@fs=44.1kHz 2's "0"
Cycle 3088/fs 1552/fs 784/fs
Init Cycle fs=44.1kHz fs=22.05kHz 70.0ms 140.0ms ( ) 70.4ms 35.2ms ( ) 17.8ms 35.6ms N/A
fs=11.025kHz 280.1ms 140.8ms 71.1ms ( N/A ) Default
N/A N/A Table 30. ADC
MS0404-J-00 - 39 -
2005/08
ASAHI KASEI
[AK5701]
pin
3 Chip address
I/F
(CSN, CCLK, CDTI)
CSP pin
CSN
1) CSP pin = "L" I/F Chip address (2bits, "10" ), Read/Write (1bit, "1" ), Register address (MSB first, 5bits) Control Data (MSB first, 8bits) CCLK "" "" CSN "" 16 CCLK "" CCLK 7MHz (max) PDN pin = "L"
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "0" "1"
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (C1 = "1", C0 = "0"); Fixed to "10" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data
Figure 41.
(CSP pin = "L")
2) CSP pin = "H" I/F Chip address (2bits, "01" ), Read/Write (1bit, "1" ), Register address (MSB first, 5bits) Control Data (MSB first, 8bits) CCLK "" "" CSN "" 16 CCLK "" CCLK 7MHz (max) PDN pin = "L"
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "0" "1" "1"
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (C1 = "0", C0 = "1"); Fixed to "01" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data
Figure 42.
(CSP pin = "H")
MS0404-J-00 - 40 -
2005/08
ASAHI KASEI
[AK5701]
Addr 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH
Register Name Power Management PLL Control Signal Select Mic Gain Control Audio Format Select fs Select Clock Output Select Volume Control Lch Input Volume Control Rch Input Volume Control Timer Select ALC Mode Control 1 ALC Mode Control 2 Mode Control 1 Mode Control 2
D7 0 0 0 0 0 HPF1 0 0 IVL7 IVR7 0 REF7 ALC TE3 0
D6 0 0 0 0 0 HPF0 0 0 IVL6 IVR6 0 REF6 ZELMN TE2 0
D5 0 PLL3 0 0 1 BCKO1 0 0 IVL5 IVR5 0 REF5 LMAT1 TE1 0
D4 0 PLL2 PMMP 0 MIX BCKO0 0 0 IVL4 IVR4 0 REF4 LMAT0 TE0 0
D3 0 PLL1 MDIF2 0 MSBS FS3 THR 0 IVL3 IVR3 ZTM1 REF3 RGAIN1 0 0
D2
PMVCM
PLL0 MDIF1 0 BCKP FS2 MCKO 0 IVL2 IVR2 ZTM0 REF2 RGAIN0 0 0
D1 PMADR M/S INR
MGAIN1
D0 PMADL PMPLL INL
MGAIN0
DIF1 FS1 PS1 0 IVL1 IVR1 WTM1 REF1 LMTH1 0
TMASTER
DIF0 FS0 PS0 IVOLC IVL0 IVR0 WTM0 REF0 LMTH0 0 0
Note 29. PDN pin Note 30. "0"
"L" "1" 10H-1EH "1" "0"
MS0404-J-00 - 41 -
2005/08
ASAHI KASEI
[AK5701]
Addr 10H
Register Name Power Management Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 PMVCM 0
D1 PMADR 0
D0 PMADL 0
PMADL: MIC-Amp Lch, ADC Lch 0: Power down (Default) 1: Power up PMADR: MIC-Amp Rch, ADC Rch 0: Power down (Default) 1: Power up PMADL PMADR bit 44.1kHz, HPF1-0 bits = "00") PMVCM: VCOM 0: Power down (Default) 1: Power up "0" PMVCM bit "1" PMVCM bit PMADL, PMADR, PMPLL, PMMP, MCKO bits "0"
"0"
"1" ADC
(3088/fs=70.0ms@fs=
ON/OFF ("1"/"0") PDN pin "L"
PMVCM, PMADL, PMADR, PMPLL, MCKO bits (typ. 1A) ADC PDN pin = "L"
"0" 20A(typ)
ADC
Addr 11H
Register Name PLL Control Default
D7 0 0
D6 0 0
D5 PLL3 1
D4 PLL2 0
D3 PLL1 0
D2 PLL0 1
D1 M/S 0
D0 PMPLL 0
PMPLL: PLL 0: EXT Mode and Power Down (Default) 1: PLL Mode and Power up M/S: Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode PLL3-0: PLL (See Table 4) Default: "1001"(MCKI pin=12MHz)
MS0404-J-00 - 42 -
2005/08
ASAHI KASEI
[AK5701]
Addr 12H
Register Name Signal Select Default
D7 0 0
D6 0 0
D5 0 0
D4 PMMP 0
D3 MDIF2 0
D2 MDIF1 0
D1 INR 0
D0 INL 0
INL: ADC Lch 0: LIN1 pin (Default) 1: LIN2 pin INR: ADC Rch 0: RIN1 pin (Default) 1: RIN2 pin MDIF1: ADC Lch 0: (LIN1/LIN2 pin: Default) 1: (LIN+/LIN- pin) MDIF2: ADC Rch 0: (RIN1/RIN2 pin: Default) 1: (RIN+/RIN- pin) PMMP: MPWR pin 0: Power down: Hi-Z (Default) 1: Power up
Addr 13H Register Name Mic Gain Control Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1
MGAIN1
D0
MGAIN0
0
1
MGAIN1-0: Default: "01"(+15dB)
Addr 14H Register Name Audio Format Select Default D7 0 0 D6 0 0
(See Table 20)
D5 1 1
D4 MIX 0
D3 MSBS 0
D2 BCKP 0
D1 DIF1 1
D0 DIF0 1
DIF1-0: Default: "11" (I2S) BCKP: DSP Mode "0": "" SDTO "1": "" SDTO BCLK/EXBCLK (Default)
(See Table 15)
(See Table 16)
MSBS: DSP Mode LRCK/EXLRCK "0": LRCK/EXLRCK "" "1": LRCK/EXLRCK "" MIX: ADC (see Table 17) "0": Normal operation (Default) "1": (L+R)/2
(See Table 16) BCLK/EXBCLK BCLK/EXBCLK 1
(Default)
MS0404-J-00 - 43 -
2005/08
ASAHI KASEI
[AK5701]
Addr 15H
Register Name fs Select Default
D7 HPF1 0
D6 HPF0 0
D5 BCKO1 0
D4 BCKO0 1
D3 FS3 1
D2 FS2 1
D1 FS1 1
D0 FS0 1
FS3-0: (See Table 5 and Table 6) Default: "1111" (44.1kHz) PLL
MCKI EXT
(See Table 11) MCKI
BCKO1-0: Default: "01" (32fs)
BCLK
(See Table 10)
HPF1-0: HPF Default: "00" (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
ADC
(Table 18, Table 30)
Addr 16H
Register Name Clock Output Select Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 THR 0
D2 MCKO 0
D1 PS1 0
D0 PS0 0
PS1-0: MCKO Default: "00"(256fs)
(Table 9)
MCKO: MCKO 0: Disable: MCKO pin = "L" (Default) 1: Enable: Output frequency is selected by PS1-0 bits. THR: 0: OFF (Default) 1: ON (Table 14)
Addr 17H
Register Name Volume Control Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 0 0
D1 0 0
D0 IVOLC 1
IVOLC: IVOL 0: Independent 1: Dependent (Default) IVOLC bit = "1"
IVL7-0 bit
IVOL
IVR7-0 bit
IVL7-0 bit
Addr 18H 19H
Register Name Lch Input Volume Control Rch Input Volume Control Default
D7 IVL7 IVR7 1
D6 IVL6 IVR6 0
D5 IVL5 IVR5 0
D4 IVL4 IVR4 1
D3 IVL3 IVR3 0
D2 IVL2 IVR2 0
D1 IVL1 IVR1 0
D0 IVL0 IVR0 1
IVL7-0, IVR7-0: Default: "91H" (0dB)
; 0.375dB step, 242 Level (Table 29)
MS0404-J-00 - 44 -
2005/08
ASAHI KASEI
[AK5701]
Addr 1AH
Register Name Timer Select Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 ZTM1 0
D2 ZTM0 0
D1 WTM1 0
D0 WTM0 0
WTM1-0: ALC Default: "00" (128/fs) ALC ZTM1-0: ALC Default: "00" (128/fs) ALC
(see Table 25)
(see Table 24)
Addr 1BH
Register Name ALC Mode Control 1 Default
D7 REF7 1
D6 REF6 1
D5 REF5 1
D4 REF4 0
D3 REF3 0
D2 REF2 0
D1 REF1 0
D0 REF0 1
REF7-0: ALC Default: "E1H" (+30.0dB)
0.375dB step, 242 Level (Table 27)
Addr 1CH
Register Name ALC Mode Control 2 Default
D7 ALC 0
D6 ZELMN 0
D5 LMAT1 0
D4 LMAT0 0
D3
RGAIN1
D2
RGAIN0
0
0
D1 LMTH1 0
D0 LMTH0 0
LMTH1-0: ALC Default: "00" RGAIN1-0: ALC Default: "00" LMAT1-0: ALC Default: "00" ZELMN: ALC 0: Enable (Default) 1: Disable ALC: ALC 0: ALC Disable (Default) 1: ALC Enable ATT
/
(see Table 22)
(see Table 26)
(see Table 23)
MS0404-J-00 - 45 -
2005/08
ASAHI KASEI
[AK5701]
Addr 1DH
Register Name Mode Control 1 Default
D7 TE3 1
D6 TE2 0
D5 TE1 1
D4 TE0 0
D3 0 0
D2 0 0
D1 0 0
D0 0 0
TE3-0: EXT Master Mode Enable "0101" 1EH EXT Master Mode "1010", "0101" Default: "1010"
"1010"
Addr 1EH
Register Name Mode Control 2 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 0 0
D1
TMASTER
0
D0 0 0
TMASTER: EXT Master Mode TE3-0 bits = "0101" 0: Except EXT Master Mode (Default) 1: EXT Master Mode
MS0404-J-00 - 46 -
2005/08
ASAHI KASEI
[AK5701]
Figure 43
Figure 44
(AKD5701)
P
18
17
16
15
14 MCKI
EXBCLK 13
CCLK
2.2k 2.2k 2.2k 2.2k
CDTI
PDN
CSN
DSP
19 MPWR External MIC 1u 1u Internal MIC 1u 1u Rp Cp 20 RIN2 21 LIN2 22 RIN1 23 LIN1 24 VCOC VCOM DVDD AVDD DVSS AVSS 0.1 x Cp (Note)
EXLRCK 12 EXSDTI 11
AK5701VN
Top View
MCKO 10 CSP SDTO LRCK BCLK 9 8 7 DSP
1
2
3
4
5 10u 0.1u
0.1u
Power Supply 2.4 3.6V
2.2u
10u 0.1u
Power Supply 1.6 3.6V
6
Analog Ground
Digital Ground
Note: - AK5701 - EXT - PLL Cp - 100ms
AVSS, DVSS (PMPLL bit = "0") (PMPLL bit = "1") VCOC pin Cp Rp Table 4 AC
Cp+Rp 1F
0.1 x
Figure 43.
(
)
MS0404-J-00 - 47 -
2005/08
ASAHI KASEI
[AK5701]
P
18
17
16
15
14 MCKI
EXBCLK 13
CCLK
CDTI
PDN
CSN
DSP
19 MPWR 20 RIN2 Line In 21 LIN2 22 RIN1 23 LIN1 24 VCOC VCOM DVDD AVDD DVSS AVSS 0.1 x Cp (Note) Rp Cp
EXLRCK 12 EXSDTI 11
AK5701VN
Top View
MCKO 10 CSP SDTO LRCK BCLK 9 8 7 DSP
1
2
3
4
5 10u 0.1u
0.1u
Power Supply 2.4 3.6V
2.2u
10u 0.1u
Power Supply 1.6 3.6V
6
Analog Ground
Digital Ground
Note: - AK5701 - EXT - PLL Cp
AVSS, DVSS (PMPLL bit = "0") (PMPLL bit = "1") VCOC pin Cp Rp Table 4
Cp+Rp
0.1 x
Figure 44.
(
)
MS0404-J-00 - 48 -
2005/08
ASAHI KASEI
[AK5701]
1. AVDD, DVDD AVDD, DVDD AVSS, DVSS PC
2. AVDD pin VCOM 2.2F 0.1F AVSS VCOM pin AVDD AVSS 0.1F
VCOM pin 3. 60k (typ)@MGAIN1-0 bits = (0.5 x AVDD) 0.6 DC 2's (2 ) HPF(fc=3.4Hz@HPF1-0 bits = "00", fs=44.1kHz) AVSS AVDD
"00", 30k (typ)@MGAIN1-0 bits = "01" or "10" x AVDD Vpp(typ)@MGAIN 1-0 bits = "00" fc=1/(2RC) DC (ADC DC AK5701
)
MS0404-J-00 - 49 -
2005/08
ASAHI KASEI
[AK5701]
ADC
Power-up
1. PLL
Example:
Power Supply
(1)
PDN pin
(2) (3)
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz
PMVCM bit
(Addr:10H, D2) (4)
(1) Power Supply & PDN pin = "L"
"H"
MCKO bit
(Addr:16H, D2)
PMPLL bit
(Addr:11H, D0) (5)
MCKI pin
(2)Addr:11H, Data:12H Addr:14H, Data:23H Addr:15H, Data:2FH
Input
M/S bit
(Addr:11H, D1) 40msec(max) (6)
(3)Addr:10H, Data:04H
BCLK pin LRCK pin
40msec(max) (8)
Output
(4)Addr:16H, Data:04H Addr:11H, Data:13H
MCKO pin
(7)
Output
MCKO, BCLK and LRCK output
Figure 45. Clock Set Up Sequence (1)
< (1)
> PDN pin "L" "H" AK5701 150ns "L" (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, M/S bits (2a) M/S bit = "1" , PLL3-0, FS3-0, BCKO1-0 (2b) DIF1-0 (3) VCOM : PMVCM bit = "0" "1" VCOM (4) MCKO : MCKO bit = "1" MCKO : MCKO bit = "0" (5) PMPLL bit = "0" "1" MCKI pin PLL MCKI=12MHz 40ms(max) (Table 4) (6) PLL BCLK, LRCK (7) MCKO bit = "1" MCKO pin (8) MCKO bit = "1" PLL MCKO pin
PLL
MS0404-J-00 - 50 -
2005/08
ASAHI KASEI
[AK5701]
2. PLL
(EXLRCK or EXBCLK pin)
Example:
Power Supply
(1)
Audio I/F Format : I2S PLL Reference clock: EXBCLK EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz
PDN pin
(2) (3)
4fs ofPower Supply & PDN pin = "L" (1)
"H"
PMVCM bit
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
(2) Addr:11H, Data:0CH Addr:14H, Data:23H Addr:15H, Data:2FH
Input
(4)
EXLRCK pin EXBCLK pin Internal Clock
(3) Addr:10H, Data:04H
(5)
(4) Addr:11H, Data:0DH
Figure 46. Clock Set Up Sequence (2)
< (1)
> PDN pin "L" "H" AK5701 150ns "L" (2) DIF1-0, FS3-0, PLL3-0 bits (3) VCOM : PMVCM bit = "0" "1" VCOM (4) PMPLL bit = "0" "1" PLL (EXLRCK or EXBCLK pin) PLL EXLRCK PLL EXBCLK PLL VCOC pin 10k+4.7nF 2ms(max) (5) PLL
PLL 160ms(max), (Table 4)
MS0404-J-00 - 51 -
2005/08
ASAHI KASEI
[AK5701]
3. PLL
(MCKI pin)
Example:
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz
Power Supply
(1)
(1) Power Supply & PDN pin = "L"
"H"
PDN pin
(2) (3)
PMVCM bit
(Addr:10H, D2) (4)
(2)Addr:11H, Data:10H Addr:14H, Data:23H Addr:15H, Data:2FH (3)Addr:10H, Data:04H
MCKO bit
(Addr:16H, D2)
PMPLL bit
(Addr:11H, D0) (5)
MCKI pin
Input
40msec(max) (6)
(4)Addr:16H, Data:04H Addr:11H, Data:11H
MCKO pin
(7) (8)
Output
MCKO output start
EXBCLK pin EXLRCK pin
Input
EXBCLK and EXLRCK input start
Figure 47. Clock Set Up Sequence (3)
< (1)
> PDN pin "L" "H" AK5701 150ns "L" (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, M/S bits (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKO : MCKO bit = "1" (5) PMPLL bit = "0" "1" MCKI pin PLL MCKI=12MHz 40ms(max) (Table 4) (6) PLL MCKO pin (7) MCKO pin (8) MCKO EXBCLK, EXLRCK
PLL
MS0404-J-00 - 52 -
2005/08
ASAHI KASEI
[AK5701]
4.
(
)
Example:
Audio I/F Format: I2S Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable
Power Supply
(1)
(1) Power Supply & PDN pin = "L"
"H"
PDN pin
(2) (3)
PMVCM bit
(Addr:10H, D2) (4)
(2) Addr:11H, Data:00H Addr:14H, Data:23H Addr:15H, Data:2FH
Input
(4)
MCKI pin EXLRCK pin EXBCLK pin
(3) Addr:10H, Data:04H
Input
MCKI, EXBCLK and EXLRCK input
Figure 48. Clock Set Up Sequence (4)
< (1)
> PDN pin "L" "H" AK5701 150ns (2) DIF1-0, FS1-0 bits (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKI, EXLRCK, EXBCLK "L"
MS0404-J-00 - 53 -
2005/08
ASAHI KASEI
[AK5701]
5.
(
)
Power Supply
(1)
PDN pin
(2) (3)
Example:
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select: 256fs Sampling Frequency: 44.1kHz
PMVCM bit
(Addr:10H, D2)
MCKI pin
Input
(1) Power Supply & PDN pin = "L"
"H"
M/S bit
(Addr:11H, D1)
TE3-0 bits
(Addr:1DH, D7-4)
"1010"
"0101"
TMASTER bit
(Addr:1EH, D1)
(2)Addr:11H, Data:26H Addr:14H, Data:23H Addr:15H, Data:2FH Addr:1DH, Data:50H Addr:1EH, Data:02H BCLK and LRCK output
BCLK pin LRCK pin
Output
(3)Addr:10H, Data:04H
Figure 49. Clock Set Up Sequence (5)
< (1) (2)
> PDN pin "L" "H" AK5701 150ns "L" DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0, TMASTER bits
(2a) M/S bit = "1", FS3-0, BCKO1-0 (2b) DIF1-0 (2c) TE3-0 bits = "0101" (2d) TMASTER bit = "1": BCLK, LRCK (3) VCOM PMVCM bit = "0" VCOM EXT Master Mode "1010"
"1"
PDN pin = "L" Table 1
"H"
TE3-0 bits =
MS0404-J-00 - 54 -
2005/08
ASAHI KASEI
[AK5701]
6.
&
Example:
Power Supply
(1)
Audio I/F Format : I2S PLL Reference clock: EXBCLK EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz
PDN pin
(2) (3)
4fs ofPower Supply & PDN pin = "L" (1)
"H"
PMVCM bit
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
(2) Addr:11H, Data:0CH Addr:14H, Data:23H Addr:15H, Data:2FH Addr:16H, Data:08H
Input
(4)
EXLRCK pin EXBCLK pin Internal Clock
(3) Addr:10H, Data:04H
(5)
(4) Addr:11H, Data:0DH
Figure 50. Clock Set Up Sequence (6)
< (1)
> PDN pin "L" "H" AK5701 150ns "L" (2) THR bit = "1" DIF1-0, FS3-0, PLL3-0 bits (3) VCOM : PMVCM bit = "0" "1" VCOM (4) PMPLL bit = "0" "1" PLL (EXLRCK or EXBCLK pin) PLL EXLRCK PLL EXBCLK PLL VCOC pin 10k+4.7nF 2ms(max) (5) PLL
PLL 160ms(max), (Table 4)
MS0404-J-00 - 55 -
2005/08
ASAHI KASEI
[AK5701]
7.
Power Supply
(1)
PDN pin
(2)
(1) Power Supply & PDN pin = "L"
"H"
THR bit
(Addr:16H, D3)
(2) Addr:16H, Data:08H
(3)
EXLRCK pin EXBCLK pin EXSDTI pin
Input
MCKI, EXBCLK and EXLRCK input
Figure 51. Clock Set Up Sequence (7)
< (1)
> PDN pin "L" AK5701 (2) THR bit = "1" (3) EXLRCK, EXBCLK, EXSDTI "H" 150ns "L"
LRCK, BCLK, SDTO
MS0404-J-00 - 56 -
2005/08
ASAHI KASEI
[AK5701]
Example:
PLL Master Mode Audio I/F Format:I2S Sampling Frequency:44.1kHz Pre MIC AMP:+15dB MIC Power On ALC setting:Refer to Figrure 37 ALC bit = "1"
(1) Addr:15H, Data:2FH
FS3-0 bits
(Addr:15H, D3-0)
X,XXX
(1)
1111
(2) Addr:12H, Data:10H Addr:13H, Data:01H
MIC Control
(Addr:12H, D4 & Addr:13H, D1-0)
0, 01
(2)
1, 01
(3) Addr:1AH, Data:0AH
Timer Control
(Addr:1AH)
XXH
(3)
0AH
(4) Addr:1BH, Data:E1H
ALC Control 1
(Addr:1BH)
XXH
(4)
E1H 81H
(5) (8)
(5) Addr:1CH, Data:81H
ALC Control 2
(Addr:1CH)
XXH ALC Disable
01H ALC Disable
(6) Addr:10H, Data:07H
ALC State PMADL/R bit
(Addr:10H, D1-0)
ALC Enable
Recording (7) Addr:10H, Data:01H
3088 / fs (6) (7)
ADC Internal State
Power Down
Initialize Normal State Power Down
(8) Addr:1CH, Data:01H
Figure 52. MIC Input Recording Sequence < > fs=44.1kHz "
ALC
ALC
"Figure 39. ALC
(1)
(FS3-0 bits)
PLL (6) (2) ( 72H&73H) (3) ALC Timer ( 7AH) (4) ALC REF ( 7BH) (5) LMTH1-0, RGAIN1-0, LMAT1-0, ALC bits ( 7CH) (6) ADC : PMADL = PMADR bits = "0" "1" ADC 3088/fs=70.0ms@fs=44.1kHz, HPF1-0 bits = "00" ALC (IVL/R7-0 bits) (0dB) 100ms PMVCM=PMMP bits = "1" 2ms PMPLL bit = "1" 6ms PMADL=PMADR bits = "1" (7) ADC : PMADL = PMADR bits = "1" "0" ADC ALC Disable ALC (ALC bit = "0") ADC (PMADL = PMADR bits = "0") PMADL = PMADR bits = "0" (IVL/R7-0 bits) (8) ALC Disable: ALC bit = "1" "0"
PLL ADC
MS0404-J-00 - 57 -
2005/08
ASAHI KASEI
[AK5701]
ADC
1. PLL
Example:
(1)
PMPLL bit
(Addr:11H, D0)
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 44.1kHz
M/S bit
(Addr:11H, D1) (2)
(1) Addr:11H, Data:10H
"H" or "L"
MCKO bit
(Addr:16H, D2)
(2) Addr:16H, Data:00H
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 53. Clock Stopping Sequence (1) < > (1) PLL (2) MCKO (3) : PMPLL=M/S bits = "1" "0" : MCKO bit = "1" "0"
2. PLL
(EXLRCK, EXBCLK pin)
Example
(1)
PMPLL bit
(Addr:11H, D0) (2)
Audio I/F Format : I2S PLL Reference clock: EXBCLK BCLK frequency: 64fs Sampling Frequency: 44.1kHz
EXBCLK EXLRCK
Input
(2)
(1) Addr:11H, Data:0CH
Input
(2) Stop the external clocks
Figure 54. Clock Stopping Sequence (2) < > (1) PLL (2) * & : PMPLL bit = "1" "0"
MS0404-J-00 - 58 -
2005/08
ASAHI KASEI
[AK5701]
3. PLL
(MCKI pin)
Example
Audio I/F Format: I2S PLL Reference clock: MCKI=11.2896MHz EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:11H, D0) (2)
(1) Addr:11H, Data:10H (2) Addr:16H, Data:00H
(3)
MCKO bit
(Addr:16H, D2)
External MCKI
Input
(3) Stop the external clocks
Figure 55. Clock Stopping Sequence (3) < > (1) PLL (2) MCKO (3) : PMPLL bit = "1" "0" : MCKO bit = "1" "0"
4.
(
(1)
)
External MCKI EXBCLK EXLRCK
Input
Example
(1)
Input
(1)
Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz
Input
(1) Stop the external clocks
Figure 56. Clock Stopping Sequence (4) < (1) * >
5.
(
(1)
)
External MCKI BCLK LRCK
Input
Example
Output Output
"H" or "L" "H" or "L"
Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz
(1) Stop MCKI
Figure 57. Clock Stopping Sequence (5) < > (1) MCKI
BCLK
LRCK
"H"
"L"
MS0404-J-00 - 59 -
2005/08
ASAHI KASEI
[AK5701]
(typ. 1A)
PMVCM bit = "0" PDN pin = "L"
20A(typ)
MS0404-J-00 - 60 -
2005/08
ASAHI KASEI
[AK5701]
24pin QFN (Unit: mm)
4.0 0.1
13 12
A
2.4 0.15
18 19
2.4 0.15
4.0 0.1
Exposed Pad
7 6
B
24
0.40 0.1
1
0.23 0.05
0.10 M
PIN #1 ID
(0.35 x 45 )
0.5
:
(Exposed Pad)
: : :
MS0404-J-00 - 61 -
0.75 0.05
0.08
0.2
2005/08
ASAHI KASEI
[AK5701]
5701
XXXX
1
XXXX : Date code identifier (4 )
Date (YY/MM/DD) 05/08/04
Revision 00
Reason
Page
Contents
*
* * *
* *
MS0404-J-00 - 62 -
2005/08

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